Technology Mapping and Placement for Delay-Minimization in LUT-Based FPGA Design

摘要

This paper presents a delay optimized technology mapping algorithm and a timing-driven placement algorithm for LUT-based FPGA. The technology mapping algorithm consists of a minimum delay mapping procedure under arbitrary net-delay model, a mapping-driven decomposition procedure for short delay and a post-processing procedure reducing the number of LUTs. It can be proved that the mapping procedure can obtain a minimum delay mapped circuit. The timing-driven placement algorithm is a constructive algorithm, which consists of three steps. The algorithm can not only reduce the designed circuit delay, but also run fast.