Novel Plating Cell Geometry for Uniform Metal Deposition

摘要

The need for smaller and faster electronic circuits is driving the design of PCB interconnects in the direction of finer pitch transmission lines, smaller diameter through holes and vias, and thicker boards with higher layer counts to provide increased circuit densities (1,2). With the advent of HDI, the number of electronic devices on a single chip is continuously increasing, and in the interest of smaller devices, so is the need for multilevel interconnect (3). Increasing utilization of multilevel interconnections, or z-interconnects, increases the importance of uniformity and desirable mechanical properties of the z-interconnect. Any voids and non-uniformities of the copper in the z-interconnects may result in deposit fatigue and deposit cracking, which may result in short circuiting and product failure (4, 5).