Delta-I Noise Suppression Techniques in Printed Circuit Boards for Clock Frequencies Over 50 Mhz

摘要

Delta-I noise suppression techniques were experimentally investigated on a 16-layer functional board up to 12 Ghz. The effect of embedded and high-frequency discrete decoupling capacitors was analyzed both in the frequency and time domains. While noise suppression capabilities of high-frequency discrete decoupling capacitors are restricted to about 250 Mhz and below, the embedded capacitance layers are observed to be effective all over the high-frequency range. Instead of using the conventional discrete fourier transform (DFT), the time domain response is obtained more efficiently by exploiting the periodicity of the delta-I noise. Time domain analysis indicates, when used with embedded capacitance layers, the additional benefit of high-frequency discrete decoupling capacitors are negligible to systems running at very high clock frequencies