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Study on Polishing Properties for Phase Change Memory

机译:相变存储器抛光性能研究

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In this paper, chemical mechanical planarization (CMP) process for GST material was studied to improve the electrical performances of sub-20nm PRAM device. The surface of GST material was dependent on the final treatment methods such as gas-phase etching and CMP. Although the GST CMP process exhibited better electrical performances for PRAM, it was very difficult to get the desirable GST CMP solutions due to the complicated GST material characteristics such as density, composition, doped component, and so on. Especially, the removal rate (RR) of GST was low for a GST film of sub-20nm PRAM device which was adopted a damascene structure. To overcome long process time for GST CMP, the combined approaches with gas-phase bulk GST etching and final GST CMP technology were suggested. The present work developed the gas-phase etching method having limited surface damage on GST film and the GST CMP process having sophisticated GST removal control with the designed GST CMP slurry. The proposed solution showed an enhanced device fluctuation performance and a 42% reduction in GST set resistivity(Rset). Keywords : PRAM, GST, CMP, Te, Residue, Density
机译:本文研究了GST材料的化学机械平坦化(CMP)方法,以改善子20nm峰值装置的电气性能。 GST材料表面取决于最终处理方法,例如气相蚀刻和CMP。尽管GST CMP工艺对PRAM具有更好的电气性能,但由于密度,组合物,掺杂组分等复杂的GST材料特性,非常难以获得所需的GST CMP溶液。特别是,GST的去除率(RR)对于采用镶嵌结构的子20nm PRAM器件的GST膜而低。为了克服GST CMP的长加工时间,提出了具有气相体积GST蚀刻和最终GST CMP技术的组合方法。本作工作开发了在GST膜上具有有限的表面损伤的气相蚀刻方法和具有设计GST CMP浆料的复杂GST去除控制的GST CMP工艺。所提出的解决方案显示了增强的器件波动性能和GST设定电阻率降低42%(RSET)。关键词:PRAM,GST,CMP,TE,残留物,密度

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