Fully Utilized and Low Memory-bandwidth Architecture Design of Variable Block-size Motion Estimation for H.264/AVC

摘要

In this paper, we present a novel VLSI architecture for variable block size motion estimation (VBSME) which not only enhances the PE utilization to 100% but also reduces the memory bandwidth to 1%~25% of the former designs with the same chip size. Based on a 16times31 search area register array (SARA) to buffer 16 rows of search area so as to increase the data reusability and two 16times16 current block register arrays (CBRA) for ping-pong mode, the design allows serial data input and parallel data processing. At the same time, it solves the problem of current block switch in all conditions. Our design was implemented by Synopsys Design Compiler with SMIC 0.18 cell library. Under a clock frequency of 200 MHz, the architecture allows real-time processing of D1 (720times480) @ 30 fps in a search range of [-32,+31] horizontally and vertically with 123.1k gates