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Fully Utilized and Low Memory-bandwidth Architecture Design of Variable Block-size Motion Estimation for H.264/AVC

机译:H.264 / AVC的可变块大小运动估计的充分利用的低内存带宽体系结构设计

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In this paper, we present a novel VLSI architecture for variable block size motion estimation (VBSME) which not only enhances the PE utilization to 100% but also reduces the memory bandwidth to 1%~25% of the former designs with the same chip size. Based on a 16times31 search area register array (SARA) to buffer 16 rows of search area so as to increase the data reusability and two 16times16 current block register arrays (CBRA) for ping-pong mode, the design allows serial data input and parallel data processing. At the same time, it solves the problem of current block switch in all conditions. Our design was implemented by Synopsys Design Compiler with SMIC 0.18 cell library. Under a clock frequency of 200 MHz, the architecture allows real-time processing of D1 (720times480) @ 30 fps in a search range of [-32,+31] horizontally and vertically with 123.1k gates
机译:在本文中,我们提出了一种新颖的VLSI架构,用于可变块大小运动估计(VBSME),它不仅可以将PE利用率提高到100%,而且还可以将相同芯片尺寸的以前设计的存储带宽降低到1%〜25% 。该设计基于一个16×31搜索区域寄存器阵列(SARA)来缓冲16行搜索区域以提高数据可重用性,并且基于两个16×16当前块寄存器阵列(CBRA)用于乒乓模式,该设计允许串行数据输入和并行数据加工。同时解决了所有情况下的电流块切换问题。我们的设计由Synopsys Design Compiler和SMIC 0.18单元库实现。在200 MHz的时钟频率下,该架构允许在12-3.1k门的水平和垂直搜索范围内[-32,+ 31]的情况下以30 fps实时处理D1(720times480)@ 30 fps

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