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Effects of dimensional scaling on the electronic transport properties of silicon nanofilms and nanowires

机译:尺寸缩放对硅纳米膜和纳米线电子传输特性的影响

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A detailed investigation focused upon evaluating the effects of dimensional cross-sectional nanoscaling of silicon features on the electronic transport properties is presented. The feature dimensions ranged from /spl sim/200 nm down to /spl sim/10 nm. This range represents transition region from bulk properties towards the onset of quantization. The structures were fabricated on silicon-on-insulator using interferometric lithography, reactive-ion-etching and thermal oxidation methods. In order to investigate the optical and electronic properties, the nanostructures were configured in a two terminal test device configuration. Characterization methods included; dark and illuminated steady-state DC measurements and optically pulsed transient time response measurements using a modified version of the Haynes-Shockley experiment for evaluating the carrier mobility as a function of scaling the feature cross-section. Results showed that the total carrier drift-diffusion dependent conduction increases as the feature cross-sectional dimensions are reduced from /spl sim/200 nm to /spl sim/10 nm due to carrier confinement effects and clear differences between 1D (nanofilms) versus 2D (nanowires) scaling effects are observed.
机译:提出了详细的研究,其重点是评估硅部件的尺寸横截面纳米尺度对电子传输性能的影响。功能尺寸范围从/ spl sim / 200 nm到/ spl sim / 10 nm。该范围代表从本体性质到量化开始的过渡区域。使用干涉光刻,反应离子刻蚀和热氧化方法在绝缘体上的硅上制造结构。为了研究光学和电子性质,将纳米结构配置为两端子测试装置配置。包括表征方法;使用改良版的Haynes-Shockley实验评估黑暗和照明稳态DC测量以及光脉冲瞬态时间响应测量,以评估载流子迁移率与缩放特征截面的关系。结果表明,由于载流子限制效应和一维(纳米薄膜)与二维之间的明显差异,随着特征截面尺寸从/ spl sim / 200 nm减小到/ spl sim / 10 nm,总的载流子漂移-扩散相关导电性增加。 (纳米线)观察到结垢效应。

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