Iterative convergence of optimal wire sizing and available buffer insertion for zero-skew clock tree optimization

摘要

In This work, based on the topology of one DME-based zero-skew clock tree, the analysis of the optimal width of one wire segment and the information of available buffers on one wire segment, an iterative convergence-based algorithm is proposed to assign the optimal width and insert available buffers onto any wire segment to reduce the clock delay. The experimental results show that our proposed OWSABI algorithm reduces 78%/spl sim/88% clock delay and 20%/spl sim/28% total load capacitance in one DME-based zero-skew clock routing tree.