In this paper, we propose a new first partial product addition (FPA) architecture with a new compressor (or parallel counter) to the CSA tree built in the process of adding partial products for improving speed in the fast parallel multiplier. The speed of calculating partial products is improved by about 20% compared with existing parallel counters using full adders. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14 ns multiplication speed for a 16/spl times/16 multiplier is obtained using 0.2 /spl mu/m CMOS technology. The architecture of the multiplier is easily adapted for pipeline design and demonstrates high speed performance.
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机译：在本文中，我们提出了一种新的第一部分乘积加法（FPA）架构，在CSA树中建立了新的压缩器（或并行计数器），该机制是在快速乘数乘法器中添加部分乘积的过程中提高速度的。与使用完整加法器的现有并行计数器相比，计算部分乘积的速度提高了约20％。新电路使用新颖的FPA架构将找到最终和的CLA位减少了N / 2。使用0.2 / spl mu / m CMOS技术可获得16 / spl倍/ 16乘法器的5.14 ns乘法速度。乘法器的体系结构很容易用于流水线设计，并显示出高速性能。
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