A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process

摘要

An area-optimized 10-bit current steering, triple-channel video DAC IP designed in 65nm, 1.2V/2.5V CMOS process is described. Each channel of DAC can drive an output load of 37.5 ohms to provide a maximum output voltage 1.278V. The measured DNL and INL at 250MHz are less than 1 LSB and 2 LSB, respectively. This DAC IP is optimized with small area for low cost embedded SOC applications. It has area of 0.22mm², which is the smallest IP in market.