A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application

摘要

Integration of RF/analog and digital circuitry imposes great challenges on Electro-Static-Discharge (ESD) circuit design. Substrate noise coupling through parasitic ESD capacitance degrades the RF/analog input signal, due to both ESD capacitance value and its non-linearity. This paper presents a new 4 kV fail-safe ESD structure, which uses a forward-biased diode to isolate the high capacitance node and uses both N/P junctions and P/N junctions to compensate voltage dependent capacitance. A 230 fF, linear ESD capacitance is achieved without sacrificing the protection capability. This ESD structure uses substrate pumping and sequential booting to trigger as an effective clamp. It also represents total protection including a CDM clamp.