A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter

摘要

An 8-bit, 40 MS/s, switched current pipeline analog-to-digital converter is presented. It employs a multiplexed architecture with tapered bit stage design and enhanced two-step circuit techniques. Implemented in a 3.3 V, 0.35 /spl mu/m CMOS process but operating internally from a 1.9 V supply, it achieves 6.4 effective number of bits and a resolution bandwidth of 5 MHz with a dissipation of 60 mW.