A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS

摘要

A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40/spl deg/C to +120/spl deg/C and /spl plusmn/15% variation in poly-poly capacitor sizes.