The authors study the efficiency of a DC test for a memory cell, which is the elementary building block for switched-current circuits. Simulations are performed on two different cells. It is demonstrated that most of the hard faults are detected using one single input test current for the basic cascode memory cell, and two reverse-sign currents for the S/sup 2/I cascode memory cell. This study is also extended taking into account different values for the short and open resistance.
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