A new Josephson /spl delta/-gate ternary-valued logic

摘要

A new Josephson circuit of multi-valued logic gate (Josephson ternary /spl delta/-gate) is proposed. The simulation result of the Josephson /spl delta/-gate circuit demonstrated the feasibility and the reliability operations, where very low power consumption, and ultra high speed switching operation have been achieved. Mathematical properties of /spl delta/-gate are introduced. The /spl delta/-gate forms a complete set (completeness) with the ternary constant set {-1, 0. 1}. Based on /spl delta/-gate, it is possible to analyze, synthesize and realize an arbitrary ternary logic function of n-input variables. An application, a ternary logic half-adder is presented, its simulation results shows reliable operation and excellent performance. Finally, the /spl delta/-gate can transfer signals from gate to gate without loss of amplitude, the /spl delta/-gate is a multiplexor and it is very effective for a MV-FPGA (multi-valued field-programmable gate arrays) building blocks.