Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics under Shock Loads

摘要

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattem recognition. The solder-joint built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal.