ADC clock jitter requirements for software radio receivers

摘要

The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.