electrostatic discharge; MOSFET; semiconductor device reliability; silicon-on-insulator; hot carriers; semiconductor diodes; semiconductor device models; electric breakdown; semiconductor device reliability; PD SOI CMOS performance; partial discharge silicon-on-insulator CMOS; complementary metal-oxide-semiconductor; ultra-thin gate dielectrics; floating body effects; hot carrier injection; time dependent dielectric breakdown; negative bias temperature instability; electrostatic discharge; partially depleted SOI substrate; self-heating; thermal runaway; lateral diode; charged device model; floating gate electrode; gate dielectric lifetime; Si;
机译:具有超薄栅极电介质的高性能PD SOI CMOS的可靠性挑战
机译:具有超薄栅极电介质的高性能PD SOI CMOS的可靠性挑战
机译:用于90/65 nm CMOS技术的高k和氮氧化物栅极电介质的挑战和性能限制
机译:高性能PD SOI CMOS具有超薄栅极电介质的可靠性挑战
机译:基于future的多金属高k栅极电介质的电气和材料特性,可用于未来的规模化CMOS技术:物理,可靠性和工艺开发。
机译:具有二维半导体通道的高性能晶体管的超钝化层的离子凝胶混合栅极电介质
机译:用于纳米级CMOS器件的超薄栅极氧化物和高k电介质的可靠性建模
机译:可靠性试验和CmOs NOR盖茨与向列相液晶失效分析技术的应用分析,