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Test and evaluation of multiple embedded mixed-signal test cores

机译:测试和评估多个嵌入式混合信号测试核心

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The simultaneous operation of multiple embedded analog test cores is investigated through experiments on a prototype integrated circuit containing eight such cores. Each core consists of a scan memory, some passive filters, and a fully synchronized integrated waveform digitizer for signal extraction. The circuit supports fully differential signal generation and digitization and employs common circuit techniques to enhance robustness to process variation. Simultaneous operation is demonstrated to achieve over 12-bits of amplitude resolution and more than 70 dB SFDR over a 20 MHz bandwidth. Matching issues are investigated, and instrument uniformity across about 250 cores is verified by measuring waveform generator offset errors, digitizer offset errors, and test core frequency response variability.
机译:通过在包含八个这样的内核的原型集成电路上进行实验,研究了多个嵌入式模拟测试内核的同时运行。每个内核都包含一个扫描存储器,一些无源滤波器和一个完全同步的集成波形数字化仪,用于信号提取。该电路支持全差分信号生成和数字化,并采用通用电路技术来增强处理变化的鲁棒性。演示了同时运行可在20 MHz带宽上实现超过12位的幅度分辨率和超过70 dB的SFDR。对匹配问题进行了研究,并通过测量波形发生器偏移误差,数字转换器偏移误差和测试核心频率响应可变性,验证了约250个核的仪器一致性。

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