A unique methodology for at-speed test of cDSP/sup TM/ and ASIC devices

摘要

This paper presents a new design to test methodology used to create at-speed system tests for complex integrated circuits. The unique approach discussed in this paper has been termed TADJUST, for Timing ADJUSTment, and offers a solution which enables the creation of robust at speed functional tests. The Tadjust approach provides a method for improving at-speed testability by using multiple dynamic timing references in the design to test flow. The at-speed testability problems, Tadjust concept, and supporting results from a cDSP(TM) design are discussed.