This paper describes a model to estimate the number of routing layers and total wirelength for a printed circuit board given the netlist, partslist, placement and board form factor. The estimation model is based on analysis of the wiring distribution on the board. The wiring distribution consists of the net distribution and net segmentation. An algorithm is presented which determines the contribution of net distribution. A statistical model has been developed to estimate net segmentation as "wrong way" routes due to obstacles and congestion on a board. Routability estimations are substituted for the routing task while searching the design space, significantly reducing the design time since routing is the most time consuming design task. These estimation techniques have been successfully applied to the board estimations of several designs, including a multiprocessor printed circuit board and the results are presented.
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