This article outlines certain results about trellis structures of linear block codes that achieve the highest speed of decoding while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. An upper bound on the number of parallel isomorphic subtrellises in a proper trellis for a code without exceeding the maximum state space dimension of the minimal trellis of the code is derived. The complexity of VLSI implementation of a Viterbi decoder based on an L-section trellis diagram for a code is analyzed and certain descriptive parameters are introduced. It is shown that a VLSI chip Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
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