This article outlines certain results about trellis structures oflinear block codes that achieve the highest speed of decoding whilesatisfying a constraint on the structural complexity of the trellis interms of the maximum number of states at any particular depth. An upperbound on the number of parallel isomorphic subtrellises in a propertrellis for a code without exceeding the maximum state space dimensionof the minimal trellis of the code is derived. The complexity of VLSIimplementation of a Viterbi decoder based on an L-section trellisdiagram for a code is analyzed and certain descriptive parameters areintroduced. It is shown that a VLSI chip Viterbi decoder based on anon-minimal trellis requires less area and is capable of operation athigher speed than one based on the minimal trellis when the commonlyused ACS-array architecture is considered
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