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Algebraic division for multilevel logic synthesis of multi-valued logic circuits

机译:多值逻辑电路的多级逻辑综合的代数除法

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Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: "identical" and "complementary" into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure.
机译:提出了多值逻辑(MVL)的多级逻辑综合的代数除法概念。首先,基于一组基本门,开发了MVL代数除法过程。通过在除法运算中引入“相同”和“互补”这两个MVL布尔属性,该过程被进一步改进为混合代数除法过程,可以获取更有效的代数除法,以促进MVL函数的多级逻辑合成。实验结果表明,平均而言,MVL函数的多级实现成本比两级实现节省了30.1%的成本,改进的混合代数除法比代数除法节省了19.4%的成本。

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