The authors present an evaluation of an innovative interlock collapsing arithmetic logic unit (ALU) in combination with several dual instruction issue processor organizations for two very different example architectures, IBM S/370 and MIPS R2000. The interlock collapsing ALU collapses execution interlocks between some integer operations as well as between address generation operations, without increasing the cycle time of the base machine. Thus, this allows two ALU, execution dependent instructions to be run in parallel, in a single cycle, instead of being executed sequentially. Results demonstrate that the overall contribution to the increase in instruction-level parallelism from the various processor organization design alternatives is remarkably similar to both the two example processors considering that the architectures are very different, and the contribution of the individual design alternatives varies.
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机译:作者针对两个非常不同的示例体系结构IBM S / 370和MIPS R2000,结合几种双指令发布处理器组织,对创新的互锁折叠算术逻辑单元(ALU)进行了评估。互锁崩溃ALU会使一些整数运算之间以及地址生成运算之间的执行互锁崩溃,而不会增加主机的循环时间。因此,这允许两个与执行有关的ALU指令在一个周期内并行运行,而不是依次执行。结果表明,考虑到体系结构非常不同,各种处理器组织设计替代方案对增加指令级并行性的总体贡献与两个示例处理器都非常相似,并且各个设计替代方案的贡献也有所不同。
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