HIGH PERFORMANCE INTERLOCK COLLAPSING SCISM ALU APPARATUS

摘要

It has three highly efficient variants of an arithmetic and logic unit to locking reduction (interlock collapsing). The running time following the critical path in each variant is reduced. In one of these variants, said execution time corresponds to the step number adder by a member with three-to-one in the case of a functional unit (bookset) current. In the other two variants, the running time is comparable to that of the adder three-on-one. It also presents the compromise adopted on complexity in the design of the said variants. The use of these allows to minimize execution time without unacceptably increase the number of hardware components.