A two-dimensional model at low-temperature for buried channel NMOS

摘要

A two-dimensional simulation program has been developed to model in detail the behavior of depletion-mode MOSFETs from liquid-nitrogen temperature (77 K) to room temperature (300 K). The differences between the low-temperature model and the room-temperature model in terms of numerical approaches are discussed. Simulation results in the linear region (VDS = 0.1 V) for applied gate voltages at subthreshold and above threshold are reported. These results are in reasonable agreement with experimental data available in the literature. Simulation results on the saturation region for a typical depletion-mode NMOS transistor are also presented.