A CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs is proposed, and its high-speed characteristics are demonstrated. The proposed lateral bipolar transistor has a structure analogous to NMOS transistors, which use a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub TMAX/, and r/sub bb/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 ns and 0.53 ns when load capacitances are 1 pF and 2 pF, respectively. These values are equal to those of conventional poly-Si emitter bipolar transistors.
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机译:提出了一种适用于低成本和高速BiCMOS LSI的CMOS兼容横向双极型晶体管,并展示了其高速特性。所提出的横向双极型晶体管具有类似于NMOS晶体管的结构,其使用源极和漏极自对准结构来形成发射极和集电极。 h / sub FE /,BV / sub CEO /,R / sub CS /,f / sub TMAX /和r / sub bb /的值分别为20、7 V,50 Omega,6.3 GHz和450 Omega , 分别。此外,两输入与非BiCMOS电路的延迟时间在卸载时为0.28 ns,在负载电容为1 pF和2 pF时分别为0.42 ns和0.53 ns。这些值等于常规的多晶硅发射极双极晶体管的值。
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