A CAD tool for circuit diagram extraction from VLSI layout cells

机译：从VLSI布局单元提取电路图的CAD工具

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The design and development of a software tool for verifying VLSI design in a layout format are presented. This tool displays the circuit diagram relative to a layout that is extracted from the layout definition file. This software tool is implemented in the C-language on the Microvax GPX/II workstation and is based on the MAGIC layout editing system.

机译：介绍了用于验证布局格式的VLSI设计的软件工具的设计和开发。该工具显示相对于从布局定义文件中提取的布局的电路图。该软件工具在Microvax GPX / II工作站上以C语言实现，并且基于MAGIC布局编辑系统。

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《》|1990年|P.817-820|共4页
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Martin; H.; Ram; R.;
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中图分类无线电电子学、电信技术 ;
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1. Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System [J] . Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA IEICE Transactions on Electronics . 1995 ,第11期

机译：通过CAD链接的EB测试系统中VLSI的CAD布局数据的连续电路提取，自动进行晶体管级性能故障跟踪
2. Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams [J] . Papadopoulou E. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2011 ,第5期

机译：通过高阶Voronoi图提取VLSI电路中断路的网络感知关键区域
3. Magic as a PC layout tool for small budget VLSI circuit design [J] . Berkes O.G., Williams R.W. IEEE Transactions on Education . 1991 ,第1期

机译：Magic作为用于小型VLSI电路设计的PC布局工具
4. A CAD tool for circuit diagram extraction from VLSI layout cells [C] . Martin H., Ram R., Institute of Electric and Electronic Engineer Midwest Symposium on Circuits and Systems . 1990

机译：来自VLSI布局单元的电路图中的CAD工具
5. A CLASS OF CELLULAR COMPUTER ARCHITECTURES TO SUPPORT PHYSICAL DESIGN AUTOMATION (VLSI LAYOUT, INTEGRATED CIRCUIT, ROUTING) [D] . RUTENBAR, ROBIN ARTHUR 1984

机译：一类支持物理设计自动化的蜂窝计算机体系结构（VLSI布局，集成电路，布线）
6. Metabopolis: scalable network layout for biological pathway diagrams in urban map style [O] . Hsiang-Yun Wu, Martin Nöllenburg, Filipa L. Sousa, 2019

机译：Metabopolis：城市地图样式的生物路径图的可扩展网络布局
7. Net-aware critical area extraction for opens in VLSI circuits via higher order Voronoi diagrams [O] . Papadopoulou, Evanthia 2011

机译：通过高阶Voronoi图提取VLSI电路中的网感知关键区域提取
8. Complexities of Layouts in Three-Dimensional VLSI (Very Large-Scale Integration) Circuits [R] . Aboelaze, M. A., Wah, B. W. 1987

机译：三维VLsI（超大规模集成电路）中布局的复杂性

A CAD tool for circuit diagram extraction from VLSI layout cells

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