A novel 4-18 GHz monolithic matrix distributed amplifier

摘要

The authors describe the design, fabrication, and performance of a 4-18 GHz matrix distributed amplifier which incorporates a novel biasing scheme enabling the amplifier to run at higher voltages while drawing only half of the current of conventional multistage amplifiers having comparable gain levels. A voltage divider is used at the input of the FET pair to derive the gate bias, ensuring that both FETs are biased at the same point. This scheme enables the stages to be connected in cascade at RF frequencies and in cascode for DC biasing, thus conserving current. The amplifier shows <13 dB gain across the frequency band using a chip area of only 1.9 mm*2.1 mm.