A 64 bit CMOS mainframe execution unit macrocell with errordetecting circuit

摘要

A 64-bit CMOS mainframe execution unit macrocell with errorndetecting circuits is proposed. It adopts a parity predicting logicnstructure in order to reduce the number of circuit stages in the ALUn(arithmetic and logic unit) critical path. By utilizing this structure,na one-bit-error detecting function is integrated. A novel CMOSnprecharged circuit is also developed to shorten the time required tonprecharge the whole circuit. Through the use of these techniques, 30%nfaster operation is achieved