A practical high-latchup immunity design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs

摘要

A practical high-latchup-immunity design methodology is proposed for high-density internal circuits in standard cell-based CMOS/BiCMOS LSIs. Both locally injected trigger current and uniformly generated trigger current were measured using a new test structure. Focusing on the difference in the well shunt resistance between local and uniform trigger currents, a practical latchup-free guideline based on an analytical model for uniformly generated trigger current in the well is presented for the periodic placement of well contacts dependent on parasitic device parameters, on generated trigger current level, and a layout pattern size.