Identification of amorphous silicon residues in a low-power CMOS technology

摘要

Abstract: A large variety of physical analysis techniques areused in the semiconductor industry to identify defectsimpacting yield or reliability. Identification of adefect often requires the combined use of severaltechniques to give a clear understanding of the defectnature. In the present study, several microscopytechniques (SEM, TEM, Analytical-TEM, AFM and FIB) havebeen intensively used to identify the origin ofresidues observed on the edge of large active areas ina low power CMOS technology. A KLA automatic inspectionsystem has been used for locating and quantifying thedefects. It has been shown that the defects are relatedto amorphous silicon residues whose origin is relatedto the gate deposition process. In the process, thepolysilicon gate is deposited in two steps. A firstthin amorphous silicon layer is deposited, throughwhich the Vt implant is done, followed by thedeposition of a thick polysilicon layer. Analysis ofdefaults showed that the residues are related to anon-uniform thin oxide layer located between the thickpolysilicon layer and the underlying thin amorphoussilicon, which halts the polysilicon gate etch. Thickernative oxide on amorphous silicon due to humidity ordrying spots is the presumed source of the thinnon-uniform oxide. Increasing the HF dip before thepolysilicon deposition eliminated almost all residues.No negative effect on the oxide quality or otherelectrical parameter has been observed. Eliminatingaltogether the amorphous-Si gate deposition process isan even more robust solution. !5