Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuitsby Pulsed Diode Laser Stimulation

摘要

In this paper, a methodology based upon laser stimulation andrna comparison of continuous wave and pulsed laser operationrnwill be presented that localizes the fault relevant sites in arnfully functional scan chain cell. The technique uses a laserrnincident from the backside to inject soft faults into internalrnnodes of a master-slave scan flip-flop in consequence ofrnlocalized photocurrent. Depending on the illuminated type ofrnthe transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ intornthe master or the slave stage of a flip-flop takes place. Thernlaser pulse is externally triggered and can easily be shifted tornvarious time slots in reference to clock and scan pattern. Thisrnfeature of the laser diode allows triggering the laser pulse onrnthe rising or the falling edge of the clock. Therefore, it isrnpossible to choose the stage of the flip-flop in which the faultrninjection should occur. It is also demonstrated that therntechnique is able to identify the most sensitive signalrncondition for fault injection with a better time resolution thanrnthe pulse width of the laser, a significant improvement forrnfailure analysis of integrated circuits.