An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs

摘要

This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or being developed for a multisite ASIC design project from the first specification up to the gate level netlist: our multi-site data management environment VHDLDevSys, our multi-use and re-use library ADK-Lib and our multi-platform VHDL/C++ simulation/verification environment PRO Verify together with the employment of formal methods.