首页> 外文会议>International VLSI Multilevel Interconnection Conference(VMIC); 20051004-06; Fremont,CA(US) >THE EFFECTS OF WAFER TOPOGRAPHY AFTER STI FILL ON CERIA SLURRY CMP FOR BEYOND 110NM GENERATION
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THE EFFECTS OF WAFER TOPOGRAPHY AFTER STI FILL ON CERIA SLURRY CMP FOR BEYOND 110NM GENERATION

机译:STI填充后晶圆地形图对110NM以上生成的Ceria Slurry CMP的影响

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摘要

As chip size shrinkage, similar to the pattern density effect, topography effect of STI structure would also strongly influence CMP performance due to STI filling process getting complication. In this paper, the STI topography effect on SiN erosion of direct ceria slurry CMP was studied on four different STI topography structures created by three different fill approaches on 110nm ground rule with AR~4 and ~8, in respectively. Besides, the performances of two kinds of ceria slurry with different selectivity of oxide to SiN were also compared.
机译:随着芯片尺寸的缩小,类似于图案密度效应,由于STI填充工艺变得复杂,STI结构的形貌效应也会强烈影响CMP性能。本文研究了三种不同的填充方法在110nm地基上AR分别为AR〜4和〜8形成的四种不同的STI形貌结构,研究了STI形貌对直接氧化铈浆料CMP SiN腐蚀的影响。此外,还比较了两种氧化物对SiN的选择性不同的二氧化铈浆料的性能。

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