首页> 外文会议>International VLSI Multilevel Interconnection Conference(VMIC); 20040930-1002; Waikoloa Beach,HI(US) >The Effect of In-Situ STI Liner Oxide on Threshold Voltage and Its Application to Enhance Yield Stability
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The Effect of In-Situ STI Liner Oxide on Threshold Voltage and Its Application to Enhance Yield Stability

机译:原位STI内衬氧化物对阈值电压的影响及其在提高良率稳定性中的应用

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摘要

Because of possessing many promising properties, shallow trench isolation (STI) using HDP (High Density Plasma) CVD oxide as trench-filling material has been widely adopted by existent ULSI technology. We have found recently that threshold voltage of MOSFET would be intensively influenced by D/S (Deposition/Sputtering) ratio of HDP tool and it will consequently lead to unstable yield performance. In light of this, we have proposed an approach to compensate the effect by in-situ depositing a thin liner oxide layer before main HDP process proceeds. Through this technique, trench corner clipping phenomenon can be modulated by changing the liner oxide thickness and stable threshold voltage and yield performance are achieved. In addition, trench-filling capability still maintains with liner oxide existence, which is vindicated by SEM micrograph with void-free filling. Most importantly, this technique is fully compatible with incumbent ULSI technology.
机译:由于具有许多有希望的特性,使用HDP(高密度等离子体)CVD氧化物作为沟槽填充材料的浅沟槽隔离(STI)已被现有的ULSI技术广泛采用。最近我们发现,MOSFET的阈值电压会受到HDP工具的D / S(沉积/溅射)比的强烈影响,因此会导致不稳定的良率。有鉴于此,我们提出了一种通过在主HDP工艺进行之前就地沉积一层薄衬里氧化物层来补偿这种影响的方法。通过这种技术,可以通过改变衬里氧化物的厚度来调节沟槽拐角削波现象,从而获得稳定的阈值电压和成品率性能。另外,通过存在衬里氧化物,沟槽填充能力仍然保持,这由具有无空隙填充的SEM显微照片证明。最重要的是,该技术与现有的ULSI技术完全兼容。

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