NOVEL WET TAPER ETCHING OF INTERCONNECTS ON LARGE AREA SUBSTRATES USING GALVANIC REACTION

摘要

We propose a novel wet taper etching process of interconnects. This can solve the poor uniformity of tapered sidewall profiles and side etch length by wet etching on a large area substrate. This is a novel wet taper etching process based on the electrochemical principle of double layer different metals. The taper etching characteristics and its advantages on the thin film transistors (TFTs) fabrications are described. A few experiments reveal its etching mechanism. Even on large area substrates, this process enables the uniform control of wet etched sidewall profiles and side etch lengths. For the gang printing of high-resolution displays, this wet etching process enables the fabrication of TFTs with conformable coverage of CVD films and accurate size patterns on a large area glass substrate.