Increasing Planarity for Failure Analysis Using Blocked Reactive Ion Etching Combined with Planar Polish

摘要

Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper will present a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. In previous technologies it was difficult to mechanically planar polish without losing the ROI (regions of interest) at the extreme edge. Recently, it has become even more difficult with the introduction of copper and new isolation materials such as CDO (carbon doped oxide) and other low K dielectrics. In the past when using the failure analysis techniques of RIE (reactive ion etching) in combination with planar polishing, an edge effect was observed. An edge effect occurs when the active device structures at the edge of the sample polish at a faster rate resulting in an angled downward slope. The effect observed in this situation is due to the higher density of active device regions next to the lower density of the scribe line structures at the edge of the sample. This density difference also accentuates the polish rate, due to variations of different materials such as copper or poly silicon compared to isolation. When using conventional RIE and planar polish, this edge effect and natural edge rounding often results in multiple layers at the ROI (see Fig. 1) and in some cases loss of ROI at the desired lower metal or poly layer. It also causes further analysis such as 1. Gate-ox defect inspection, 2. SEM inspection for defects, (Pico-probing) 3. Atomic Force Microscopy and poly CD measurements to become either more difficult or impossible if the ROI is lost. As microprocessor critical dimensions become smaller and the silicon more densely populated with thinner layers of gate-oxide, there is an increased need for the analysis listed above. Hence, preparation such as deprocessing becomes increasingly important. For example, it is critical to obtain a planar polish though the salicide but not exceeding the poly silicon prior to selective etch of the poly for gate-oxide defect inspection.