NON-DESTRUCTIVE POST-ANNEAL CHARACTERIZATION OF SOURCE/DRAIN PROCESSES USING THE CARRIER ILLUMINATION~(TM) METHOD

摘要

The Carrier Illumination~(TM) (CI) method provides a rapid, nondestructive, small spot size measurement of the electrically active depth of ultra-shallow junctions (USJ). The intended application is in-line process control. This paper briefly describes the measurement principles and surveys key results both in the characterization of CI in CMOS process flows and the extension of CI to ultra-thin silicon layers formed using laser thermal annealing (LTA) or chemical vapor deposition (CVD), and amorphous layers used in pre-amorphizing implants (PAI). Work with annealed implants has shown correlation to SIMS junction depth, activated dose, and electrical performance of transistors. Most significant is the correlation of extension depth measured immediately after anneal to drive current and off-state leakage measured at electrical probe, showing CI can be used to measure the universal curve of transistors well before electrical measurements are possible. More recently, extensions of the method have been developed. It has been shown that CI provides a dose-independent measurement of amorphous layer depth for PAI used in conjunction with USJ processes. CI has also been used to characterize LTA processes, showing onset of the melt and electrical activation, α-crystal interface defect annealing, and junction motion as a function of anneal energy. Beam uniformity is found through use of high-resolution scans]. Additional work has been done with CVD-Si layers, showing depth sensitivity to <150 A and depth resolution of about 1 A, and validating the theory that predicts a cosine response function with respect to depth.