Wafer Yield Estimation Using Support Vector Machines

摘要

Wafer yield estimation is a very complicated nonlinear problem due to many variations in fabrication processes at different silicon foundries. The purpose of this paper is to use Support Vector Machines (SVMs) to analyze and predict electrical test data, which are traditionally captured by probing each chip on the wafer. The predicted data produced by the support vector machines is then compared with the known measured data to determine the accuracy. Once the SVM has captured nonlinear relationship between fabrication processes and wafer yields, it can be used to predict wafer yield in other lots fabricated by the same silicon foundry. The advantage of using this approach is to save time due to probing hardware constraints, predict wafer yield across the same fabrication process and give an alternative method of device simulation. Our experiments show that the SVMs predict more accurate than classical device physics equations and in some cases SPICE simulation software in comparison with the actual measured electrical data. Electrical data used for this research include threshold voltages, saturation currents, and leakage currents.