首页> 外文会议>International Symposium on Microelectronics; 20050925-29; Philadelphia,PA(US) >Evaluation of Electroless Ni-Au Finishes for Wirebonding on PWBs
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Evaluation of Electroless Ni-Au Finishes for Wirebonding on PWBs

机译:用于PWB上的化学键合的化学镀Ni-Au涂层的评估

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Direct chip attach techniques are becoming more prevalent among higher end printed wiring board (PWB) assemblies. Chip-On-Board (COB) packaging with wirebonds, and flip chip packaging both require advanced metal finishes for the printed wiring boards that are used to achieve the higher levels of integration in today's electronic assemblies. This metallization needs to reliably withstand the multiple temperature cycles inherent to the assembly process. This paper examines how wirebondability is affected by variations in the surface finish thickness. At the Johns Hopkins University Applied Physics Laboratory, the finish metallization employed for COB applications is Cu-Ni-Au. The starting copper layer is the standard half ounce foil (18 microns thick) that is bonded to thepolyimide PWB laminate from the manufacturer. After typical PWB processing has been completed, electroless nickel and electroless gold layers are deposited on the patterned copper traces. Common plating thicknesses for Ni can range from 2.5 to 10 microns and for Au the range is 0.5 to 1.5 microns. These ranges are too wide and poor wirebondability has been observed on boards with thin plating. Excessively thick plating will increase the cost of the board with no benefit to bonding. Design of experiments and statistical analysis techniques were used to examine the effects of the nickel and gold film thicknesses, assembly temperatures, temperature cycles, and time at temperature on the initial wirebondability of the board and final reliability of the wirebonds. Failure analysis was also performed on the boards to determine the cause of the poor wirebondability and wirebond failures. The results show that optimum nickel and gold thickness can be determined for various applications.
机译:在高端印刷电路板(PWB)组件中,直接芯片连接技术变得越来越普遍。带有引线键合的板载芯片(COB)封装和倒装芯片封装都需要对印刷线路板使用先进的金属表面处理,以实现当今电子组件中更高的集成度。这种金属化需要可靠地承受组装过程固有的多个温度循环。本文研究了表面光洁度厚度的变化如何影响引线键合性。在约翰霍普金斯大学应用物理实验室,用于COB应用的精加工金属是Cu-Ni-Au。起始铜层是标准的半盎司箔(18微米厚),该箔与制造商的聚酰亚胺PWB层压板粘合在一起。完成典型的PWB处理后,将化学镀镍和化学镀金层沉积在图案化的铜迹线上。 Ni的常见镀层厚度范围为2.5到10微米,Au的范围为0.5到1.5微米。这些范围太宽,在薄镀板上观察到的可焊性差。镀层过厚会增加板的成本,而对粘接没有好处。实验和统计分析技术的设计用于检查镍和金膜的厚度,装配温度,温度循环和温度时间对板的初始引线键合性和引线键合最终可靠性的影响。还对电路板进行了故障分析,以确定造成引线键合性和引线键合不良的原因。结果表明,可以为各种应用确定最佳的镍和金厚度。

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