Iterative Capacity Allocation and Production Flow Estimation for Scheduling Semiconductor Fabrication

摘要

This paper presents an effective algorithm of determining daily production targets and the corresponding machine capacity allocation for semiconductor wafer fabrication. The algorithm adopts an iterative scheme and each iteration consists of two modules: the proportional Target Generation and Machine Allocation (TG&MA) and the Stage of Penetration Estimation Algorithm (SOPEA). In TG&MA, machine capacities are allocated to processing different types of products at various stages in proportion to their respective available workloads. With the capacity allocated to each product type, SOPEA then applies a recursive, deterministic queuing analysis to estimate the expected flow-in workload of a stage within a day. The flow-ins are fed into TG&MA for another iteration of capacity allocation. Field implementation of this algorithm has demonstrated significant effects on production move increase, cycle time reduction and line balancing.