Dual-Modulus Prescalar Implementation Using Clock Suppression

摘要

In this paper we present a new implementation of a CMOS dual modulus prescalar, a major component of the frequency synthesizer. A variable frequency division/count in conventional prescalars is achieved by feeding back of the complement the output from either the last or penultimate flip-flop stage in a shift register configuration. In this paper, we employ suppression or swallowing of a clock pulse at a predetermined state to obtain the necessary count. Preliminary studies show that the proposed scheme consumes less power than conventional design with a slight decrease in the frequency of operation. Circuit implementation of the scheme is currently being performed and the results will be presented in the conference.