Low-Power CMOS Fully-Folding ADC with a Novel Bit Synchronization Architecture

摘要

A 6-bit 250MHz low-power CMOS folly-folding analog-to-digital converter is designed in a 0.5μm standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one. A novel bit synchronization architecture also based on folding circuits is presented to reduce the number of comparators for bit synchronization and simplify the logic design. The total power dissipation is 34mW at a 5V supply.