Efficient VLSI Design and Implementation of Integer Motion Estimation for H.264 SDTV Encoder

摘要

In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several hardware-reduction techniques are investigated and a Sot-SAD-Tree VLSI structure based on SAD-Tree is proposed. Using this Sot-SAD-Tree structure, the whole data path width is reduced to 50%, and the H.264 encoder with large frame and complex motion vector can be VLSI implementation with acceptable hardware cost. Finally, a complete H.264 SDTV integer motion estimation VLSI architecture with 16×256 parallelism is designed and implemented.