The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads

摘要

The authors have been developing the CUE-v2 microprocessor performing both as dataflow and as superscalar using common pipeline resource. The CUE-v2 can simultaneously process two orthogonal types of threads, i.e., dataflow and control-flow threads, at instruction level. Its instruction fetch unit basically gives priority to dataflow thread(s), while it guarantees the minimal instruction issue opppotu-nity of a control-flow thread in order to avoid blocking. That is, it basically allocates empty slots, caused by the execution of dataflow threads, to a control-flow thread. By this means, the CUE-v2 retains the advantages of dataflow architectures, e.g., fair multiprocessing with no context switching overheads, and achieves the speedup of sequential processing by combining a superscalar execution mode. The basic design of the CUE-v2 seems to have many similar components to that of superscalar machines. However, an instruction fetch unit and the scheme of dynamic out-of-order scheduling differ considerably due to the simultaneous instruction fetch/execution of two kinds of threads. This paper first describes the architecrural design, and then quantifies its hardware amount and its design complexity using a standard cell library for a TSMC 0.18 μm process. Consequently, we found that the CUE-v2 can perform the simultaneous processing of dataflow and control-flow threads with less than 10% increase of additional hardware compared to a superscalar processor.