STEPPER SCHEDULING IN SEMICONDUCTOR WAFER FABRICATION PROCESS

摘要

In this paper, we propose an approach for scheduling bottleneck machines called steppers in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8-hour shift, determining which types of lots to work on each machine. A heuristic two-phase algorithm is developed. In the first phase, to satisfy the given target cycle time within the fab, we determine the target Work-In-Process(WIP) level at each layer. In the second phase, a mixed integer programming model for allocating the steppers is formulated. For this step, we test three heuristic algorithms for solving the machine allocation problem with the objective of keeping the actual WIP levels close to the target WIP levels after the current shift. Numerical tests show that one of the proposed heuristics using linear programming relaxation of MIP generates schedules within 5% of the optimum values on average.