Scientific Research Institute of System Analysis, Russian Academy of Sciences, 117218, Nakhimovsky prosp. 36/1, Moscow, Russia;
Scientific Research Institute of System Analysis, Russian Academy of Sciences, 117218, Nakhimovsky prosp. 36/1, Moscow, Russia,Dept. of Micro- and Nanoelectronics of Moscow Engineering Physics Institute (National Research Nuclear University), 115409, Kashirskoye shosse 31, Moscow, Russia;
Scientific Research Institute of System Analysis, Russian Academy of Sciences, 117218, Nakhimovsky prosp. 36/1, Moscow, Russia,Dept. of Micro- and Nanoelectronics of Moscow Engineering Physics Institute (National Research Nuclear University), 115409, Kashirskoye shosse 31, Moscow, Russia;
Single event transient (SET); SET tolerance; layout; SPICE SET simulation;
机译:减少低于100 nm内容可寻址存储电路中的软错误的脆弱性
机译:集成电路中软错误的电路级建模
机译:商业集成电路中的软错误
机译:Sub-100 NM集成电路中软误差的布局感知模拟
机译:在非晶衬底和用于3D集成电路的高性能亚100 nm薄膜晶体管上的纳米图形引导的单晶硅生长。
机译:PCSIM:与Python完全集成的神经电路并行仿真环境
机译:通过软件故障注入研究信号处理电路软错误的仿真平台