FPGA circuits for a Monte-Carlo based matrix inversion architecture

摘要

A Monte-Carlo based matrix inversion algorithm is optimized to develop an architecture that inverts a matrix of size 64 x 64 The architecture fits in FPGA Virtex-II devices and runs at a frequency over 200 MHz. It is observed that architecture practical prototypes for matrices of large sizes is not severely constrained by FPGA computational resources but by FPGA pin-out count. The study suggests to include the Markov generator in hardware to reduce the pin-out count overhead, reducing the complexity when partitioning large problems for hardware-software co-designs in favor of higher performance.