Signal Processing using Reconfigurable System-on-Chip Platforms

摘要

Reconfigurable System-on-Chip Platforms (RSPs) are an emerging class of adaptive architectures. The main advantage of RSPs over conventional DSPs is that the user can configure the underlying hardware based on the application. Moreover, the hardware can be reconfigured at runtime, facilitating efficient execution of multi-function applications. In this paper, key challenges in mapping applications onto RSPs are identified and a mapping methodology is proposed. Mapping signal processing applications onto RSPs and optimizing their performance is a new research area spawned by the large performance/flexibility architecture space provided by RSPs. A mapping methodology is proposed that facilitates rapid application development. Our methodology combines a high-level abstraction of the performance/flexibility space of RSPs with performance analysis of execution alternatives early in the design cvcle. Using our methodology, time performance results are demonstrated for FIR, 2D-FFT, and matrix multiplication. Significant speed-up is demonstrated compared with optimized implementations on state-of-the-art DSP, FPGA, and microprocessor platforms.